The Workshop on Design and Architectures for Signal and Image Processing (DASIP) provides an inspiring international forum for the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems.
The workshop program will include keynote speeches and contributed paper sessions.
The DASIP 2025 proceedings will be published in the Springer LNCS Series and made available on the Springer Link website.
Selected papers of DASIP 2024 and DASIP 2025 will be invited to submit an extended version of their work to Elsevier's Journal of System Architecture (JSA).
Venue
The 18th Workshop on Design and Architectures for Signal and Image Processing (DASIP 2025) will take place in conjunction with the HiPEAC 2025 conference in Barcelona, Spain, January 20 - 21, 2025.
Importante Dates
Paper submission: October 14November 04November 22, 2024 (EXTENDED, FINAL) Notification of acceptance: December 16, 2024 Camera ready submission: January 10, 2025
All deadlines are in Anywhere on Earth (AoE)
Call for Papers
Prospective authors are invited to submit manuscripts on the following topics, but not limited to them.
Custom embedded, edge and cloud architectures and systems
Machine learning and deep learning architectures for inference and training
Systems for autonomous vehicles: cars, drones, ships and space applications
Image processing and compression architectures
Smart cameras, security systems, behaviour recognition
Edge and cloud processing: special routing, configurable co-processors and low energy considerations
Real-time cryptography, secure computing, financial and personal data processing
Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computing
Biological data collection and analysis, bioinformatics
Personal digital assistants, natural language processing, wearable computing and implantable devices
Global navigation satellite and inertial navigation systems
Design Methods and Tools
Design verification and fault tolerance
Embedded system security and security validation
System-level design and hardware/software co-design
High-level synthesis, logic synthesis, communication synthesis
Embedded real-time systems and real-time operating systems
Rapid system prototyping, performance analysis and estimation
Formal models, transformations, algorithm transformations and metrics
Development Platforms, Architectures and Technologies
Embedded platforms for multimedia and telecommunication
Many-core and multi-processor systems, SoCs, and NoCs
Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
Memory system and cache management
Asynchronous (self-timed) circuits and analog and mixed-signal circuits
Authors Information
Submission Guidelines
Authors should prepare their full papers (up to 12 pages) and/or short papers (up to 6 pages, intended for work-in-progress with promising results and/or students at the early stages of their research) in the single-column Springer LNCS format. The Instructions for Proceedings Authors and the Spinger LNCS template in various formats are available through the following link: https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines The Springer’s proceedings LaTeX templates are also available in Overleaf.
Submitted papers are required to describe original unpublished work and must not be under consideration for publication elsewhere. Submissions must be fully anonymous, but authors should not hide previous work, instead, they need to make self-references in the third person.
Each submission will receive at least three independent double blind reviews from the members of the scientific committee. Authors are encouraged to take the reviewers’ comments into account when preparing the final versions of their papers and present the research during the workshop.
All accepted papers must be presented by one of the authors in order to be included in the workshop proceedings.
Please be aware that for each accepted paper, at least, one of the authors must pay the full registration fee in order for the paper to be included in the workshop proceedings and scheduled in the program.
Distinguished Speakers
Jose Nunez-Yanez
Prof. Nunez-Yanez is a professor in hardware architectures for Machine Learning at Linköping University, Sweden since 2022 within the WASP program in autonomous systems. He holds a PhD in hardware-based parallel data compression from the University of Loughborough, UK. Previously to joining Linköping University he was a reader (associate professor) at Bristol University, UK. He spent several years working in industry at ST Micro (Milan, Italy), ARM (Cambridge, UK) and Sensata Systems (Swindon, UK) with Marie Curie and Royal Society fellowships. His main area of expertise is in the design of hardware architectures and heterogeneous systems for signal processing and machine learning with a focus on run-time adaptation, high-performance via parallelism and energy-efficiency.
Title: Hardware-Aware Adaptive Quantization in Graph Neural Networks for inference and training at the edge.
Abstract: In this talk, we introduce a hardware approach for on-device training and inference targeting fully quantized and sparse graph neural networks (GNNs). The system supports both graph convolutional (GCN) and attention (GAT) networks with a hardware accelerator consisting of a dataflow architecture optimized for sparse data representations and adaptive fixed-point numeric precision. GATs are considered as GCNs extended with an attention mechanism that modifies the graph connectivity on-the-fly to focus attention on different parts of the input improving performance on certain applications. During training, the architecture widens the data path in the backward pass to maintain the gradient accuracy needed for backpropagation. In contrast, in the forward pass, the accelerator narrows the data path to emulate the uncertainty introduced by the quantized parameters. In the talk, we will discuss how this approach is particularly suited to reconfigurable and heterogenous devices and the performance and energy benefits.
Raúl Regada Alvarez
Raúl Regada Alvarez, MSc. Telecommunication Engineering (2001) and Post-Graduate in Satellite Communications (2006), both at Universidad Politécnica de Madrid. In 2000 he joined the Space division of Alcatel as electronics design engineer, becoming project technical manager in 2002. In 2007, together with the firm change to Thales Alenia Space, Raúl developed responsibilities of Project Management for satellite embarked units in all space markets. 2009 meant the return back to engineering as Head of the Avionic and Data processing design and testing engineering group. Finally in 2016 he moved his position to Product Manager of satellite on board Electronic Products for all market segments from high-end satellites to ‘smallsats’. Raúl is fully engaged with the dissemination of technology and knowledge participation as speaker in regular lectures at MSc. Degree of Systems engineering and Scientific Instruments in Space, school and college presentations and though participation in different working groups at COIT / AEIT (Spanish Telecommunication Engineers Associations).
Title: Trends in Space Implementation of Deeptech for signal and data processing.
Abstract: The space sector has been always considered one of the most innovative and top technological. However this approach relies on the difficulties and harsh environment that the satellites and spacecrafts must suffer. The massive processing is just now reaching the space sector due to the huge amount of data generated and / or directly available ‘on the edge’, this fact is facing a set of obstacles to overcome to properly behave under this environment. A wide set of opportunities are opening on the space sector, directly linked to the specific segment and quality approach selected, from the application of AI on the large missions where the reliability is a must to the low end segment where solitions try to mimic ground architectures but with major constraints on power or performances. The future is open to major innovations where the new products will be natively compatible with cloud computing, edge computing, AI and other deeptech. To conclude it is worth to mention that intrinsically the processing in space is clean and green once overcomed the launch process.
Alfonso Rodríguez Universidad Politécnica de Madrid, Madrid, Spain
Andrea Pinna Sorbonne University, Paris, France
Diana Goehringer TU Dresden, Dresden, Germany
Jean-Pierre David Ecole Polytechnique de Montreal, Montreal, Canada
João M. P. Cardoso University of Porto, Porto, Portugal
Karol Desnos INSA Rennes - IETR laboratory, Rennes, France
Marek Gorgoń AGH University of Science and Technology, Kraków, Poland
Michael Huebner Brandenburg University of Technology, Cottbus-Senftenberg, Germany
Miguel Chavarrías Universidad Politécnica de Madrid, Madrid, Spain
Paolo Meloni University of Cagliari, Cagliari, Italy
Pierre Langlois Ecole Polytechnique de Montreal, Montreal, Canada
Sebastien Pillement University of Nantes - IETR, Nantes, France
Sergio Petruz TU Dresden, Dresden, Germany
Tomasz Kryjak AGH University of Science and Technology, Kraków, Poland
Technical Program Committee
Andrea Pinna Sorbonne Univeristy, France
Andrés Otero Universidad Politécnica de Madrid, Spain
Arnaldo Oliveira Universidade de Aveiro - DETI / Instituto de Telecomunicações, Portugal
Bertrand Granado Sorbonne Université, France
Christian Pilato Politecnico di Milano, Italy
Christopher Claus Robert Bosch GmbH,
Daniel Chillet IRISA/ENSSAT University of Rennes 1, France
Diana Goehringer TU Dresden, Germany
Dimitrios Soudris National Technical University of Athens, Greece
Eduardo de La Torre Universidad Politécnica de Madrid, Spain
Francesca Palumbo Information Eng. Unit - PolComIng - University of Sassari, Italy
Frank Hannig Friedrich-Alexander University Erlangen-Nürnberg, Germany
Gabriel Caffarena University CEU San Pablo, Spain
Gustavo Marrero Callico Universidad de Las Palmas de Gran Canaria, Spain
Guy Gogniat Université de Bretagne Sud - UEB, France
Jean Francois Nezan INSA Rennes, IETR laboratory, France
Jean Pierre David Ecole Polytechnique de Montréal,
Joao Cardoso University of Porto, Portugal
João Canas Ferreira University of Porto, Portugal
Jorge Portilla Universidad Politécnica de Madrid, Spain
Kevin J. M. Martin Lab-STICC - Université de Bretagne-Sud,
Marek Gorgon AGH University of Science and Technology, Poland
Martin Danek Daiteq s.r.o., Czechia
Mateusz Komorkiewicz IEEE, Poland
Maxime Pelcat IETR/INSA, France
Milos Drutarovsky Technical University of Kosice, Slovak Republic
Nuno Roma Universidade de Lisboa, Portugal
Olivier Romain University of Cergy Pontoise, France
Oscar Gustafsson Linköping University, Sweden
Paolo Meloni University of Cagliari, Italy
Ruben Salvador CentraleSupélec - IETR, France
Sebastien Pillement University of Nantes - IETR, France
Tomasz Kryjak AGH University of Science and Technology, Poland
Yannick Le Moullec Tallinn University of Technology, Estonia
Francesco Ratto Università degli Studi di Cagliari, Italy
Claudio Rubattu University of Sassari, Italy
Georgios Zervakis University of Patras, Greece
Prior Editions
DASIP is a long-running annual workshop open to the presentation and discussion of the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems.
It was organized for the first time in 2007 in Grenoble, France, and since then it has alternated between several countries in Europe and Canada. The last five editions were co-located with HiPEAC.
DASIP 2024
In conjunction with the 19th HiPEAC Conference
Munich, Germany January 17-19
Website
DASIP 2023
In conjunction with the 18th HiPEAC Conference
Toulouse, France January 16-18
Website
DASIP 2022
In conjunction with the 17th HiPEAC Conference
Budapest, Hungary June 20-22
Website
DASIP 2021
In conjunction with the 16th HiPEAC Conference
Virtual Conference, Online January 18-20
Website
DASIP 2019
Polytechnique Montréal, Canada October 16-18
Website
DASIP 2018
University of Porto, Portugal October 10-12
Website
DASIP 2017
Technical University of Dresden, Germany September 27-29
DASIP 2016
RISA/INRIA Rennes, France October 12-14
DASIP 2015
AGH University of Science and Technology, Poland September 23-25
DASIP 2014
Technical University of Madrid, Spain October 8-10
DASIP 2013
University of Cagliari, Italy October 8-10
DASIP 2012
Karlsruhe Institute of Technology, Germany October 23-25
DASIP 2011
Tampere University of Technology, Finland November 2-4
DASIP 2010
University of Edinburgh, UK October 26-28
DASIP 2009
Sophia Antipolis, France September 22-24
DASIP 2008
Brussels, Belgium November 24
DASIP 2007
Grenoble, France November 27-29
Sponsors
Keynote
To be announced
To be announced,
Abstract: To be announced
Short bio:
Keynote
Orbiting the Edge and Stars: Bridging the gap between Space Avionics and Edge Computing, challenges and space mission's needs
David González-Arjona, GMV
Abstract: The keynote will bring the space mission processing challenges and opportunities where high-performance computing and architectural designs are pivotal role. The presentation bridges the gap between space avionics and edge computing realities, illustrating how the challenges faced in space are relevant and interconnected with the challenges encountered for other industries edge computing. Space missions are strongly based in remote processing capabilities in autonomous manner. Communications to ground may be costive, not continuous, limited in bandwidth or with big latencies for real-time actuation needs. Earth Observation and space-based sensors are generating and consuming bigger amount of data and edge computing facilitates communication reduction and real-time executions. Exploration missions and landing operations in other solar system celestial bodies autonomously may impose high-performance solution challenges into avionics electronics that must be reliant and enduring harsh environmental conditions. Fault Tolerant HW/SW architectures and technology robust against cosmic radiation, extreme temperature gradients and mechanical vibrations may limit performance capabilities. Last but not least, machine learning applications are entering more and more in the mission's algorithms, including computing challenges to get the functional benefits desired. Continual learning possibilitites will deal with uncertainties in the explored scenario but also expose avionics towards architectural challenges. These topics will be presented and discussed including examples and roadmaps for key technology for the near future in space.
Short bio: David González-Arjona holds the position of Space Equipment section head in GMV Aerospace & Defence SAU, Madrid (Spain), and he is a part-time Associate Professor in the Electronics and Communications Technologies department of Autonoma de Madrid University.
Keynote
January 18 | 10:15 - 11:00
Chair: Paola Busia, Università degli Studi di Cagliari, Italy
Orbiting the Edge and Stars: Bridging the gap between Space Avionics and Edge Computing, challenges and space mission's needs
David González-Arjona
Session #1
January 18 | 11:30 - 13:00
Chair: Tomasz Kryjak, AGH University of Science and Technology, Poland
A highly configurable platform for advanced PPG analysis
Flavie Durand De Gevigney, Julien Heulot, Eric Bazin, Jean-François Nezan, Mickaël Dardaillon and Slaheddine Aridhi
sEMG-based Gesture Recognition with Spiking Neural Networks on Low-power FPGA
Matteo Antonio Scrugli, Gianluca Leone, Paola Busia and Paolo Meloni
Scalable FPGA Implementation of Dynamic Programming for Optimal Control of Hybrid Electrical Vehicles
Frans Skarman and Oscar Gustafsson
Session #2
January 18 | 14:00 - 15:30
Chair: Alfonso Rodríguez, Universidad Politécnica de Madrid, Spain
Wordlength Optimization for Custom Floating-point Systems
Quentin Milot, Mickaël Dardaillon, Justine Bonnot and Daniel Ménard
An Initial Framework for Prototyping Radio-Interferometric Imaging Pipelines
Sunrise Wang, Nicolas Gac, Hugo Miomandre, Jean-Francois Nezan, Karol Desnos and Francois Orieux
Scratchy: A Class of Adaptable Architectures with Software-Managed Communication For Edge Streaming Applications
Joseph Faye, Naouel Haggui, Florent Kermarrec, Kévin Martin, Shuvra Bhattacharyya, Jean-François Nezan and Maxime Pelcat
Special Session
January 19 | 10:00 - 11:00
Chair: Tiago M. Dias, ISEL-IPL/INESC-ID, Portugal
Embedded AI for Image and Signal Processing: Future Challenges?
Andrea Pinna, Université Sorbonne, France
Marek Gorgon, AGH University of Science and Technology, Poland
Paolo Meloni, University of Cagliari, Italy
Session #3
January 19 | 11:30 - 12:45
Chair: Karol Desnos, INSA Rennes - IETR laboratory, France
Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications
Chilankamol Sunny, Satyajit Das, Kevin Martin and Philippe Coussy
Improving the Energy Efficiency of CNN Inference on FPGA using Partial Reconfiguration
Zhuoer Li and Sébastien Bilavarn
Optimising Graph Representation for Hardware Implementation of Graph Convolutional Networks for Event-based Vision
Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut, Andrea Pinna and Tomasz Kryjak
